This technology introduces a hardware-accelerated, distributed Quantum Low-Density Parity-Check (LDPC) decoder implemented on FPGA, designed to optimize the Union–Find decoding algorithm for scalable, high-throughput quantum error correction. By leveraging multiple BRAM banks to eliminate read/write contention and using a pipelined merge engine alongside parallel hardware update units, the architecture achieves real-time, low-latency decoding suitable for next-generation quantum processors. The solution is validated at the prototype stage with a co-simulation verification pipeline integrating Stim, Python, and Verilog to simulate quantum noise models accurately.